Owing to their high integration density, extremely low quiescent leakage current and ever improving power handling capacity, power MOSFETs continue their popular adoption in power electronics such as switching power supplies and converters. Some of the highly important attributes of power MOSFETs are their continuously shrinking packaged size and accompanying increased heat dissipation driven by the consumer market.
As a result, power semiconductor device packages with dual side cooling (top and bottom side) are required in many high-power density applications in order to minimize the device operating temperature thus maximize the device and system reliability and efficiency. Bottom side cooling has been achieved by mounting the semiconductor chips on metallic leadframes or heat conductive substrates, or by incorporating thermal vias if laminated circuit substrates are used. The following briefly reviews some prior arts for achieving top side cooling.
In a so-called “DirectFET” approach (U.S. Pat. Nos. 6,624,522, 7,285,866, US Patent Application Publication 2007/0284722), the semiconductor die(s) are required to be mounted upside down inside a metal can such that the backside of die(s) which is typically the drain of a discrete power MOSFET is in electrical contact with a “lid” of the can. The metal can acts like a drain connection to the back of the die, a “lid” as well as a “top side” heat sink for top side cooling. On the other hand, source and gate electrodes on the actual top side of the die are facing down and connected to a circuit board which acts as a bottom heat sink surface. Thus, with the “DirectFET” approach, its external geometrical connections, or package footprint, are not configured to conform to an industry standard package pin out such as, for example, the SO-8 package footprint.
In U.S. Pat. No. 6,777,800 entitled “Semiconductor die package including drain clip”, A drain clip having a major surface is electrically coupled to the drain region of the semiconductor die. A non-conductive molding material encapsulates the die. The major surface of the drain clip is exposed through the non-conductive molding material for top side cooling. However, this packaging approach requires a flip-chip configuration that complicates the die packaging process.
The following briefly reviews some prior arts using top side plate bonding with plate exposure for achieving top side cooling while achieving package footprints that conform to an industry standard package pin out.
U.S. application Ser. No. 11/799,467 disclosed a semiconductor package having dimpled plate interconnections. FIG. 17 and FIG. 18 of U.S. application Ser. No. 11/799,467 are respectively reproduced here as FIG. 1A and FIG. 1B and briefly described. Thus, with reference to FIG. 1A and FIG. 1B, a source plate 1700 includes a plurality of dimples 1710 formed thereon. The dimples 1710 are concave with respect to a top surface 1715 of the source plate 1700 and include a through hole 1720 having an opening 1725 formed beyond a plane of a bottom surface 1730 thereof. Similarly, a gate plate 1750 includes a dimple 1760 that is concave with respect to a top surface 1755 of the gate plate 1750 and includes a through hole 1770. This package is compatible with industry standard package pin outs, however this package does not achieve top side cooling.
In U.S. Pat. No. 6,249,041 entitled “IC chip package with directly connected leads” by Kasem et al, hereafter referred to as U.S. Pat. No. 6,249,041, an improved semiconductor device is disclosed that includes a semiconductor chip with contact areas on the top or bottom surface. FIG. 3B of U.S. Pat. No. 6,249,041 is reproduced here and labeled as FIG. 2 and briefly described. A power MOSFET package 41 constructed is shown in cross sectional view. The power MOSFET package 41 has a power MOSFET chip 42a powered by common contact areas. A source contact area and a gate contact area on the top side of chip 42a are each covered with a metallization layer formed from a conductive metal. Likewise, a drain contact area on the bottom side of chip 42a is covered with a metallization layer. A source lead assembly has a contact area 48a in contact with the source contact area on chip 42a. Contact area 48a on source lead assembly is held in contact with source contact area on chip 42a by an electrically conductive adhesive layer 49. Three source leads 48b extend from contact area 48a to provide electrical contact with a printed circuit board. Like source lead assembly, a gate lead assembly also has a contact area in contact with gate contact area on chip 42a. Similarly, a drain lead assembly has a contact area 52a in contact with the drain contact area on the bottom side of chip 42a and four drain leads 52b extending from contact area 52a to provide electrical contact with the printed circuit board. Contact area 52a on drain lead assembly is held in contact with the drain contact area on chip 42a by an electrically conductive adhesive layer 53. A plastic encapsulant 54 encapsulates chip 42a, contact areas 48a and 52a of lead assemblies, and portions of leads 48b and 52b of lead assemblies. Encapsulant 54 provides electrical and thermal insulation of chip 42a from the outside world, as well as giving structural support and rigidity to the power MOSFET package 41. However this package also does not achieve top side cooling.
In U.S. Pat. No. 4,935,803 entitled “Self-centering electrode for power devices” by Kalfus et al, hereafter referred to as U.S. Pat. No. 4,935,803, an improved means and method for forming leads to a power device is disclosed by use of a one-piece leadframe on which the die is mounted and a separate connecting clip between the leadframe and the bonding pad on the semiconductor die. FIG. 4 of U.S. Pat. No. 4,935,803 is reproduced here and labeled as FIG. 3. In cross-sectional view, die 16 having contact region 22 surrounded by raised dielectric 18, is mounted on die flag 13 by attachment means 20. Attachment means 20 may be conductive or insulating, but conductive solder is frequently used when die support 12, 13 is also intended to serve as one of the electrical leads of the device coupled to die 16. Lead 30 is provided extending toward die 16 and is intended to serve as an external connection to die 16. Conveniently located near the end of lead 30, closest to die 16 is alignment means 32, 52. In the example shown, alignment means 32 has the shape of a depression in lead 30 but other shapes such as a protrusion could also be used. In FIG. 3, alignment means 32 has the shape of a substantially hemi-cylindrical groove or other rounded two dimensional shapes whose long dimension extends transverse to the direction from lead 30 toward die 16. While alignment means 32, 42 are shown as being convex downward, they could also be convex upward, i.e., bumps or protrusions rather than depressions. Connection means or clip 40 extends from lead 30 to contact region 22 on die 16. Connection means 40 is attached to lead 30 and die contact 22 by bonding material 36 and 38, respectively. Connection clip or means 40 has alignment means 42 at a first end which mates with alignment means 32 of lead 30 and, at a second end, has attachment means 46 having bottom 48 which is coupled to die contact or bonding pad 22. The shapes of alignment means 42 are such that they engage alignment means 32. The groove shaped depressions of alignment means 32 and 42 permit connection means 40 to move transverse to the direction extending from lead 30 toward die contact 22 on die 16, but restrain movement of clip 40 relative to lead 30 and die contact 22 in the direction toward die contact 22 and restrain horizontal (azimuthal) rotation of connection means 40 relative to lead 30 or bonding pad 22. However, connection means 40 is able to rotate during assembly in the vertical plane. This is desirable since it permits substantial variations in the thickness of die 16 to be accommodated with no change in the leadframe or connection means. This simplifies manufacturing. The configuration shown in FIG. 3 is particularly useful for this purpose because the nested curved surfaces of alignment means 32, 42 form a rotary hinge which permits vertical rotation of connection means 40 relative to lead 30 without substantial change in the spacing of alignment means 32, 42. In this respect it is also desirable that the end of connection means 40 which attaches to bonding pad 22 also be curved, as illustrated by attachment means 46. U.S. Pat. No. 4,935,803 also does not achieve top side cooling.
In US Patent Application 20080087992 entitled “Semiconductor package having a bridged plate interconnection” by Shi Lei et al, hereafter referred to as US 20080087992, a semiconductor package with a bridged source plate interconnection is disclosed for packaging a semiconductor die. FIG. 7 and FIG. 5 of US 20080087992 are reproduced here and respectively labeled as FIG. 4A and FIG. 4B. In FIG. 4A is illustrated a semiconductor package 700 includes a leadframe 705 having a die pad 107, a source contact portion 110 and a gate contact portion 115. A power semiconductor die 120 may have a metalized drain area (not shown) coupled to the die pad 107 by solder reflow. A bridged source plate 130 includes a metal plate stamped or punched to form a bridge portion 131, valley portions 133 on either side of the bridge portion 131, plane portions 135 on either side of the valley portions 133 and the bridge portion 131, and a connection portion 137 depending from one of the plane portions 135. Bridged source plate 130 includes a pair of dimples 710 formed in respective valley portions 133. The dimples 710 are concave with respect to a top surface 720c of the valley portions 133 and have bottom surfaces (not shown) extending beyond a plane of a bottom surface thereof. A gate plate 750 electrically connects the gate contact portion 115 of the gate lead 117 to a gate metalized contact area (not shown) on the power semiconductor die 120. A gate plate dimple 760 is positioned and stamped or punched on the gate plate 750 so as to align with the gate metalized contact of the semiconductor die 120 during solder reflow. The gate plate dimple 760 can optionally include a through hole 770. FIG. 4B illustrates a preferred embodiment of US 20080087992 that is a semiconductor package 500 including a top surface 510 of the bridged source plate bridge portion 131 exposed through an encapsulant 520c. The exposed top surface 510 provides for thermal dissipation of heat generated by the power semiconductor die 120. In addition, the exposed top surface 510 provides an attachment surface for an additional heat sink for additional heat dissipation. Flow of encapsulant material under the bridge portion 131 provides for increased mechanical strength of the package 500.
In a commonly assigned U.S. patent application Ser. No. 12/130,663 with filing date May 30, 2008 and entitled “CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/130,663, a semiconductor device package with a conductive clip having separate parallel conductive fingers electrically connected to each other by conductive bridges is disclosed. FIG. 2A and FIG. 2D of U.S. application Ser. No. 12/130,663 are reproduced here and respectively labeled as FIG. 4C and FIG. 4D. FIG. 4C illustrates a semiconductor device package 200 with its gate bond wire replaced with a gate clip 208. The device package 200 includes a fused lead frame 102, a MOS device 114 having top source, top gate and bottom drain located on top of the lead frame 102 and a clip 112 having separate parallel conductive fingers 104 electrically connected to each other by conductive bridges 106. The clip 112 is electrically bonded to the top source of the MOS device 114 only at the bridges 106. The fingers 104 may exhibit a bend out of the plane of the clip 112 in order to vertically contact with the fused source lead 118. In this embodiment, the top gate is electrically connected to the gate lead 110b of the lead frame 102 by a gate clip 208. The top surface of the gate clip 208 and the top surface of the clip 112 are coplanar in this example. FIG. 4D is a perspective view of the semiconductor device package 200 after covered with molding compound 216. As shown in FIG. 4D, the top surface of the clip 112 and the gate clip 208 are exposed.
In a commonly assigned U.S. patent application Ser. No. 12/237,953 with filing date Sep. 24, 2008 and entitled “Top Exposed Clip with Window Array” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/237,953, a semiconductor device package with single stage clips is disclosed. Each single stage clip includes a metal sheet having arrays of windows thereon. FIG. 1A and FIG. 1B of U.S. application Ser. No. 12/237,953 are reproduced here and respectively labeled as FIG. 4E and FIG. 4F. As shown in FIG. 4E, the semiconductor device package 100 includes a fused lead frame 102 and a semiconductor device 104a having contact regions on top and bottom surfaces. By way of example, the semiconductor device 104a may be a vertical metal oxide semiconductor (MOS) device having a top source contact S, a top gate contact G and a bottom drain contact D. In this example, the semiconductor device 104a is located on top of the lead frame 102 with the bottom drain contact D facing and making electrical contact with the main portion of the lead frame 102. By way of example, the lead frame 102 may be fused or non-fused. As an embodiment of U.S. application Ser. No. 12/237,953, the semiconductor device package 100 includes single stage clips 106a, which include two separate metal sheets 108 and 110a having arrays of windows 111 and 113 respectively. Here, metal refers to a material that is thermally and electrically conductive, and preferably is malleable. In metal sheet 108, arrays of conductive fingers, each of which includes a first end and a second end, are formed to make electrical contact with the source contact region S of the semiconductor device 104a at the second end of the conductive finger. The first end of each of the conductive fingers is electrically connected to the metal sheet 108 at each of the corresponding windows 111. This configuration provides for multiple electrically parallel paths that are separated from each other. One or more additional conductive fingers may be formed from a separate metal sheet 110a to provide electrical contact between the gate contact region G of the semiconductor device 104a and gate leads 107a of the lead frame 102. Each of the conductive fingers includes a first end electrically connected to the metal sheet 110a at a window 113 and a second end formed to make electrical contact with the gate contact region G of the semiconductor device 104a. Electrical and mechanical contact between the conductive fingers and contact regions S, G may be established, e.g., through the use of a solder or conductive adhesive. As shown in FIG. 4F, the semiconductor device package 100 may be encapsulated with molding compound 118a and leave the tops of the metal sheets 108, 110a exposed. The exposed area is large and allows for efficient heat dissipation. However, the contact area to the semiconductor device 104a is small.
While the above cited prior arts using top side plate bonding technology with plate exposure do offer numerous advantages like:                Compatibility with industry standard package pin out        Elimination of bond wires thus reducing production cost        Reduction of parasitic inductance and resistance        Lowering package thermal resistance        
All of them can only achieve limited effectiveness of top side cooling when heat-sinks are put in direct contact with the top of the package due to the limited amount of top metal exposed through the plastic encapsulation compound. Each of them exhibits a trade off between maximizing the top metal exposed for heat dissipation and maximizing the metal connecting the top side die electrodes to leads. More specifically, as the number of top side die electrodes and/or the number of top side plate features of lower elevation (dimples, anchor holes, plane portions, valley portions, conductive bridges between fingers, windows) increase the available area for exposed top surface of each top side plate for heat dissipation correspondingly decreases causing further degradation of effectiveness of top side cooling. Therefore, it remains highly desirable to further enhance the effectiveness of top side cooling while optimizing connection to the semiconductor die and maintaining a semiconductor device packaging footprint that conforms to an industry standard package pin out.